1. Field of the Invention
The present invention relates to a reference voltage generating circuit, and more particularly, to a reference voltage generating circuit with high accuracy.
2. Description of the Prior Art
In the fields of digital-to-analog converters (DAC) and analog-to-digital converters (ADC), the allowance range of amplitudes of an input signal is determined according to the relative voltage levels of the positive and negative reference voltages. The noise standard of each circuit in an ADC or DAC is also determined by the allowance range of amplitudes of an input signal. In other words, the larger the relative level of the reference voltage is, the less the design complexity of the noise demands is.
The relative reference voltage levels generated inside the IC, however, are lower than those generated outside the IC. Therefore, in general, the external voltage source VDD and the ground voltage GND are often utilized to generate needed reference voltages.
Please refer to FIG. 1, which is a diagram of a conventional reference voltage generating circuit 100. As shown in FIG. 1, the reference voltage generating circuit 100 includes a capacitor CREF, an external capacitor COFF, and two switches SW1 and SW2. The connections between these components are shown in FIG. 1 and a detailed description is thus omitted here. However, in the following disclosure, the operation of the reference voltage generating circuit 100 is illustrated.
In a first stage, the switch SW1 is turned on and the switch SW2 is turned off. The capacitor CREF samples the external voltage source in the first stage. In a second stage, the switch SW2 is turned on and the switch SW1 is turned off. The capacitor CREF redistributes charges with the external capacitor COFF. The first stage and the second stage are alternatively performed such that the capacitor CREF acts as a resistor. Therefore, the reference voltage generating circuit 100 can be regarded as an RC filtering circuit utilized to filter out noises of the external voltage source. This also means a clean reference voltage VREF (i.e. the noise in the reference voltage VREF is substantially eliminated) can be generated.
If the aforementioned reference voltage generating circuit 100 is utilized in the sigma-delta DAC or sigma-delta ADC, for the reference voltage generating circuit 100 has to utilize the same capacitor CREF to perform the sampling operation in the first stage and generate the reference voltage VREF in the second stage, as well as the first stage and the second stage correspond to only half of the sampling period of the input signal of the sigma delta modulator, the operational clock which is originally utilized in the sigma-delta ADC (DAC) does not correspond to the first and second stages. Therefore, two additional operational clocks, which can point out the first stage and the second stage, have to be generated for the reference voltage generating circuit 100. In this way, the complexity of the entire circuit can raise, and a high sampling frequency cannot be utilized.